1. Field of the Invention
The present invention relates to a system and an apparatus for synchronization capable of preventing performance degradation due to latency increase in multi-clock domain environment, a synchronization failure detecting circuit, and a data receiving method.
2. Description of the Related Art
In designing a system for a chip (SoC) using intellecture properties (IP), each IP may be operated at different clock frequencies. When designing to integrate different IPs, synchronization failure in transmitting data between the IPs should be considered. For example, when all the IPs are operated by a single clock in order to meet the IPs operated at the lowest clock frequency, synchronization is guaranteed but causes performance degradation. The clock period of each IPs is controlled to have an integer multiple relations, which can prevent performance degradation while using a relatively easier synchronization method, as compared with a single clock-based synchronization method. However, in order to control integer multiple relation between the clocks, the number of IPs should be increased or the difference in the inter-IP optimized clock frequencies should be increased, such that the application fields of the synchronization method are greatly reduced.
In order to resolve the problem of synchronization failure, various synchronization methods have been proposed.
A “synchronous” method is commonly assumed to mean “synchronous” circuit-based and it is assumed that the clock characteristics over the entire area in a chip should be the same. A “mesochronous” method is assumed to mean the difference in the clock frequencies observed in chips is not allowed but the difference in phases is allowed. In other words, the mesochronous is based on the assumption that only the delay time from the clock source to two specific leaf nodes is different, and the delay elements controlling the clocks or the data transfer speed should be used for synchronization. Meanwhile, a “plesiochronous” method recognizes the difference in fine frequencies and thus, the phases can be also changed. This means the “plesiochronous” method is based on the assumption that it repeatedly performs synchronization using the “mesochronous” method.
“Related” is based on the assumption that two points of the clock frequency in a chip has the integer multiple relations. By following the above based assumptions, synchronization failure cases can be easily predicted by the characteristic analysis of the clock frequency. At this time, a “heterogeneous” method uses the synchronous failure predicting method that variously specializes the clock frequency without using the integer multiple relations between the clock frequencies. An “asynchronous” method is based on the assumption including all the foregoing assumptions, but requires a synchronization apparatus based on an asynchronous design method for the synchronization.
The “synchronous”, “mesochronous”, and “plesiochronous” methods are classified under the single clock environment while the “related”, “heterogeneous”, and “asynchronous” assumptions are classified under the personal multi-clock environment when the clock sources are in plural. The methods up to the “heterogeneous” methods should maintain the periodicity of all the clocks.